This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-197795, filed Jun. 30, 2000, and No. 2001-175616, filed Jun. 11, 2001, the entire contents of both of which are incorporated herein by reference.
This invention relates to a semiconductor device having a rigid capacitor structure and a method for fabricating the same and more particularly to the structure of cell capacitors and fuse capacitors of a semiconductor memory device.
The development of the fine patterning technique of recent semiconductor devices is significant. Particularly, the fine patterning technique for DRAMs (Dynamic Random Access Memories) is increasingly developed. Therefore, the following subjects become important.
(1) How to form capacitors having sufficiently large capacitances in a limited area which becomes smaller as the area occupied by the memory cells becomes smaller.
(2) How to maintain the manufacturing yield to the same degree as the former generation with the progress of generations of integration.
The subject (1) can be coped with by using a cylinder structure for a cell capacitor, for example. The cylinder structure is one type of stacked capacitor and attains a large surface area while suppressing the occupied area by 3-dimensionally forming a cylindrical capacitor.
Further, as the technique for solving the subject (2), much attention is paid to the redundancy technique. The technique is attained by previously forming fuse elements in the semiconductor device in order to compensate for semiconductor elements which become partly defective. If the semiconductor element becomes defective, a fuse element corresponding to the defective portion is cut off to replace the defective semiconductor element by a spare semiconductor element, thus enhancing the manufacturing yield as a whole chip.
As the fuse elements, laser fuses in which information corresponding to the defective portion is written by fusing (laser-blowing) a metal interconnection layer by application of laser have been widely used. However, in recent years, electrical fuses for electrically cutting off or short-circuiting fuse elements have received much attention. As one type of the electrical fuse, an anti-fuse using the capacitor structure is provided. In the anti-fuse, information is written by applying high voltage to the fuse structure (fuse capacitor) to break down the insulating film and electrically short-circuiting the fuse capacitor. In the DRAM, the anti-fuse starts to be used in the redundancy technique for replacing the defective memory cell by a redundancy memory cell. Generally, the anti-fuse is formed by the same process as that for forming the cell capacitor structure.
The conventional DRAM structure is explained with reference to FIG. 1. FIG. 1 is a partial cross sectional view showing a DRAM using double-surface-cylinder type stacked capacitors.
As shown in FIG. 1, element isolation regions 11 are formed in a memory cell array area A1 and peripheral area A2 in a silicon substrate 10 and a gate insulating film 12 is formed on the silicon substrate 10. The xe2x80x9cmemory cell array areaxe2x80x9d indicates an area in which memory cells of a DRAM are formed and the xe2x80x9cperipheral areaxe2x80x9d indicates an area in which anti-fuses are formed. Gate electrodes 13 are formed on the gate insulating film 12 and MOS transistors are formed by selectively forming impurity diffused layers (not shown) functioning as a drain region and source regions in the silicon substrate 10. The MOS transistors are used as cell transistors in the memory cell array area A1. Further, an interlayer insulating film 15 for covering the MOS transistors and a silicon oxide (SiO2) film 16 are sequentially formed on the gate insulating film 12. Bit lines 17 connected to corresponding drain regions of the cell transistors in areas (not shown) are formed in the interlayer insulating film 15 of the memory cell array area A1 and interconnection layers 17 connected to corresponding drain regions of the MOS transistors are formed in the peripheral area A2. Further, contact plugs 18 connected to the source regions of the cell transistors in the memory cell array area A1 and the MOS transistors in the peripheral id area A2 are formed in the interlayer insulating film 15 and silicon oxide film 16. Then, double-surface-cylinder type capacitor lower electrodes 20 are formed on the silicon oxide film 16 so as to be connected to corresponding contact plugs 18. An interlayer insulating film 22 is formed in an area on the silicon oxide film 16 in which no capacitor lower electrode 20 is formed. Capacitor insulating films 24 are respectively formed on the capacitor lower electrodes 20. Capacitor upper electrodes 25 are formed on the capacitor insulating films 24 to respectively form cell capacitors and fuse capacitors in the memory cell array area A1 and peripheral area A2. Further, an interlayer insulating film 27 is formed on the capacitors and a metal interconnection layer 29 is formed on the interlayer insulating film 27 to form a DRAM.
FIG. 2A is a plane pattern of the capacitors of the above DRAM. In this example, a case wherein the DRAM is a 256-Mbit DRAM designed according to the 0.13 xcexcm rule is shown.
As shown in FIG. 2A, cell capacitors 61 formed on an interlayer insulating film 60 are arranged at an interval of approx. 0.52 xcexcm in the bit line direction and at an interval of approx. 0.26 xcexcm in the word line direction. On the other hand, fuse capacitors 62 are arranged at an interval of approx. 1 xcexcm and are generally arranged at an interval larger than at least twice the interval of the cell capacitors 61. Thus, the cell capacitors in the memory cell array area A1 are arranged in a large-scale array form and the fuse capacitors in the peripheral area A2 are arranged in a small scale configuration of single bit to several bits in many cases. This is because the plate electrodes (upper electrodes) of the cell capacitors 61 are commonly connected, but all of the plate electrodes of the fuse capacitors 62 must be independently connected. Further, this is because high voltage for breaking down the fuse capacitors is applied to interconnections connected to the plate electrodes of the fuse capacitors, and therefore, it becomes necessary to use metal interconnections with large width.
With the above double-surface-cylinder type capacitor, since the bottom surface, inner peripheral surface and outer peripheral surface of the cylinder can be used as an electrode surface, the capacitance of the capacitor can be made large.
As a material of the capacitor insulating film of the conventional cell capacitor and fuse capacitor, a silicon oxide film is used. Further, a polysilicon film is used as a material of the capacitor electrode and an HSG (Hemi-Spherical Grained) silicon film is used to attain a larger surface area.
In recent years, attempts have been made to increase the capacitance of the capacitor by using a high-dielectric-constant material, for example, a tantalum oxide (Ta2O5) film having a larger dielectric constant in comparison with the silicon oxide film to form the capacitor insulating film. It is known that an element such as ruthenium in the platinum group is preferably used as a material of the capacitor electrode if the high-dielectric-constant material is used to form the capacitor insulating film.
However, elements belonging to the platinum group have poor adhesion with respect to a silicon oxide film generally used as an interlayer insulating film. Therefore, it is difficult to deposit and form a capacitor lower electrode by use of the platinum group element. Further, since the capacitor lower electrode is stripped from the peripheral interlayer insulating film after forming the capacitor lower electrode, the structure becomes fragile and the cylinder falls in some cases. In addition, a contact portion between the contact plug and the capacitor lower electrode tends to be cut off or partly damaged to have high resistance.
As explained with reference to FIG. 2A, the fuse capacitors are arranged at the larger interval in comparison with the cell capacitors. That is, the design rules of the capacitors in the memory cell array area and peripheral area are greatly different from each other. For example, when a trench portion used for forming a capacitor is formed in the interlayer insulating film, the lithography condition is set to match with the condition in the memory cell array area in which the design rule is strict. Then, the capacitor forming process in the peripheral area cannot be optimally set. Specifically, the diameter of the trench portion in the peripheral area becomes smaller than the designed one, for example, and the size control becomes difficult. If the diameter of the trench portion used for forming an anti-fuse becomes smaller, an amount of material gas introduced into the trench portion when the capacitor lower electrode is formed by use of a CVD (Chemical vapor Deposition) method is reduced. Then, the film thickness of the capacitor lower electrode becomes smaller, and as a result, the capacitor lower electrode 20 tends to fall as shown in FIG. 2B. Further, since the film thickness of the capacitor lower electrode 20 becomes smaller particularly in the bottom portion, a pin hole or the like is formed in the lower electrode 20. Then, the contact plug 18 is also etched in the later wet etching step in some cases. If the above defect occurs, the anti-fuse cannot be practically used and dust is caused on the wafer, thereby causing the manufacturing yield to be significantly lowered.
A semiconductor device according to an aspect of the present invention comprises a contact plug formed in a first interlayer insulating film on a semiconductor substrate; a second interlayer insulating film formed on the first interlayer insulating film and having an opening reaching the first interlayer insulating film, said contact plug being exposed to the bottom surface of the opening; a liner film formed on bottom and side surfaces of the opening; a stacked capacitor lower electrode formed to be at least partly filled in the opening, said capacitor lower electrode being formed in contact with said first and second interlayer insulating films with said liner film disposed therebetween and said capacitor lower electrode being formed of a platinum group material; a capacitor insulating film formed on the capacitor lower electrode, said capacitor insulating film being formed of a high-dielectric-constant material; and a capacitor upper electrode formed on said capacitor insulating film; and wherein a portion of said liner film which is formed on the side surface of the opening formed in said second insulating film is recessed by a depth equal to the film thickness of said capacitor insulating film from the opening end face of the opening and a recessed portion is filled with said capacitor insulating films.
A method for fabricating a semiconductor device according to an aspect of the present invention comprises the steps of forming a first interlayer insulating film on a semiconductor substrate; forming a contact plug in the first interlayer insulating film; forming a second interlayer insulating film on the first interlayer insulating film; forming a trench portion having a depth to reach the first interlayer insulating film in the second interlayer insulating film, the contact plug being exposed to the bottom surface of the trench portion; forming a liner film on the bottom and side surfaces of the trench portion; forming a capacitor lower electrode on the liner film, recessing the liner film disposed between the second interlayer insulating film and the capacitor lower electrode from the upper surface of the second interlayer insulating film; forming a capacitor insulating film on the capacitor lower electrode, the capacitor insulating film being formed to fill an area of the liner film recessed from the upper surface of the second interlayer insulating film; and forming a capacitor upper electrode on the capacitor insulating film; wherein the step of recessing the liner film is to recess the liner film from the upper surface of the second interlayer insulating film by at least a depth equal to the film thickness of the capacitor insulating film.